View STEL-1109_195872.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STEL-1109 Data Sheet
STEL-1109/CR
5 - 65 MHz Burst Transmitter
R
TABLE OF CONTENTS
TRADEMARKS................................................................................................................................................................ KEY FEATURES................................................................................................................................................................ INTRODUCTION............................................................................................................................................................ PIN CONFIGURATION ................................................................................................................................................. POWER SUPPLY PINS.................................................................................................................................................... FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS............................................................................................ Overview ........................................................................................................................................................................ Data Path Description ................................................................................................................................................... Bit Sync Block ............................................................................................................................................................. Bit Encoder Block....................................................................................................................................................... Data Path Control (Multiplexers)........................................................................................................................ Scrambler ................................................................................................................................................................ Reed-Solomon Encoder......................................................................................................................................... Symbol Mapper Block............................................................................................................................................... Bit Mapper.............................................................................................................................................................. Differential Encoder .............................................................................................................................................. Symbol Mapper...................................................................................................................................................... Nyquist Fir Filter ....................................................................................................................................................... Interpolating Filter .................................................................................................................................................... Modulator ................................................................................................................................................................... 10-Bit DAC.................................................................................................................................................................. Control Unit Description.............................................................................................................................................. Bus Interface Unit ...................................................................................................................................................... Clock Generator ......................................................................................................................................................... NCO............................................................................................................................................................................. TIMING DIAGRAMS..................................................................................................................................................... Clock Timing.................................................................................................................................................................. Pulse Width .................................................................................................................................................................... Bit Clock Synchronization............................................................................................................................................ Input Data and Clock Timing...................................................................................................................................... Write Timing .................................................................................................................................................................. Read Timing ................................................................................................................................................................... NCO Loading (User Controlled) ................................................................................................................................. NCO Loading (Automatic) .......................................................................................................................................... Digital Output Timing .................................................................................................................................................. DATAEN to DATAENO Timing ................................................................................................................................ BURST TIMING EXAMPLES........................................................................................................................................ Burst Timing: Full Burst (Slave Mode, QPSK) .......................................................................................................... Master Mode, BPSK Burst Timing Signal Relationships ......................................................................................... Slave Mode, BPSK Burst Timing Signal Relationships ............................................................................................ Master Mode, QPSK Burst Timing Signal Relationships ........................................................................................ Slave Mode, QPSK Burst Timing Signal Relationships ........................................................................................... Master Mode, 16QAM Burst Timing Signal Relationships .................................................................................... Slave Mode, 16QAM Burst Timing Signal Relationships........................................................................................ ELECTRICAL SPECIFICATIONS ................................................................................................................................ RECOMMENDED INTERFACE CIRCUITS .............................................................................................................. Slave Mode Interface..................................................................................................................................................... Master Mode Interface.................................................................................................................................................. EXAMPLE OUTPUT LOAD SCHEMATIC ................................................................................................................ MECHANICAL SPECIFICATIONS ............................................................................................................................. 4 5 6 7 7 8 8 9 9 10 10 11 12 13 13 14 15 18 19 20 20 20 20 20 21 23 23 23 24 25 26 27 28 28 29 30 30 31 32 32 33 33 34 34 35 38 38 38 39 39
STEL-1109
2
PRELIMINARY PRODUCT INFORMATION
LIST OF ILLUSTRATIONS
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16.
STEL-1109 Block Diagram.................................................................................................................... Bit Encoder Functional Diagram ........................................................................................................ Scrambler Block Diagram .................................................................................................................... DAVIC Scrambler.................................................................................................................................. Mapping Block Functional Diagram .................................................................................................. BPSK Constellation ............................................................................................................................... QPSK Constellation .............................................................................................................................. Natural Mapping Constellation.......................................................................................................... Gray Coded Constellation ................................................................................................................... Left Coded Constellation ..................................................................................................................... DAVIC Coded Constellation ............................................................................................................... Right Coded Constellation .................................................................................................................. Nyquist FIR Filter.................................................................................................................................. Interpolation Filter Block Diagram..................................................................................................... Duty Cycle Derating Versus Temperature (@3.3v).......................................................................... STEL-1109 Mechanical Characteristics ..............................................................................................
9 10 11 12 13 15 16 16 17 17 18 18 19 19 36 39
PRELIMINARY PRODUCT INFORMATION
3
STEL-1109
LIST OF TABLES
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31.
STEL-1109 Features .............................................................................................................................. I/O Signal Pin Assignments................................................................................................................ STEL -1109 Configuration Register Data Fields............................................................................... Data Latching Options ......................................................................................................................... Bit Encoding Data Path Options......................................................................................................... Scrambler Parameters .......................................................................................................................... Sample Scramble Register Values ...................................................................................................... Reed-Solomon Encoder Parameters................................................................................................... Bit Mapping Options............................................................................................................................ Differential Encoder Control............................................................................................................... Qpsk Differential Encoding and Phase Shift .................................................................................... Symbol Mapping Selections................................................................................................................ Symbol Mapping .................................................................................................................................. FIR Filter Configuration Options ....................................................................................................... FIR Filter Coefficient Storage.............................................................................................................. Interpolation Filter Bypass Control.................................................................................................... Interpolation Filter Signal Level Control .......................................................................................... Signal Inversion Control...................................................................................................................... FCW Selection ....................................................................................................................................... Clock Timing AC Characteristics ....................................................................................................... Pulse Width AC Characteristics ......................................................................................................... Bit Clock Synchronization AC Characteristics ................................................................................. Input Data and Clock AC Characteristics ......................................................................................... Write Timing AC Characteristics ....................................................................................................... Read Timing AC Characteristics ........................................................................................................ NCO Loading AC Characteristics ...................................................................................................... Digital Output Timing AC Characteristics ....................................................................................... DATAEN to DATAENO Timing AC Characteristics...................................................................... Absolute Maximum Ratings ............................................................................................................... Recommended Operating Conditions ............................................................................................... DC Characteristics ................................................................................................................................
5 7 8 9 11 11 12 13 14 14 15 16 17 18 18 19 19 20 22 23 23 24 25 26 27 28 29 30 35 36 37
TRADEMARKS
Stanford Telecom and STEL are registered trademarks of Stanford Telecommunications, Incorporated.
(R) (R)
STEL-1109
4
PRELIMINARY PRODUCT INFORMATION
KEY FEATURES n Complete BPSK/QPSK/16QAM modulator in n n n n n
a CMOS ASIC Programmable over a wide range of data rates NCO modulator provides fine frequency resolution 165 MHz maximum clock rate generates a modulated carrier at frequencies programmable from 5 to 65 MHz Operates in continuous and burst modes Differential Encoder, Programmable Scrambler, and Programmable Reed-Solomon FEC Encoder
n n n n n n
Programmable 32-tap FIR Filter for signal shaping before modulation 10-bit DAC implemented on chip Complete upstream modulator solution - serial data in and RF signal out Compatible with DAVIC, IEEE 802.14 (preliminary), Intelsat IESS-308, ITU J.83 Annex A, MCNS Standards Supports low data rates for voice applications and high data rates for wideband applications Small Footprint, Surface Mount 80-Pin MQFP Package
Feature Carrier frequency: Symbol rate:
Table 1. STEL-1109 Features Characteristic 5 to 65 MHz (maximum of approximately 40% of master clock) From Master clock divided by 16 down to Master clock divided by 16384 (in steps of 4) yielding a maximum symbol rate of 10Msps with a 160 MHz clock. 32 programmable taps (10 bits each), symmetric response BPSK, QPSK, or 16QAM Eight selectable bit-to-symbol mappings Five selectable symbol-to-constellation mappings Signs of I and Q plus the mapping to Sine and Cosine carriers is programmable. Selectable on/off Two selectable generator polynomials Block length shortened any amount Error correction capability T = 1 to 10
FIR filter tap coefficients: Modulation: 16QAM constellation: I and Q modulator signs / Spectral Inversion Reed-Solomon encoder:
Scrambler:
Selectable on/off Self-synchronizing or frame synchronized (sidestream) Location before or after RS Encoder Programmable generator polynomial Programmable length up to 224 - 1 Programmable initial seed
Differential encoder:
Selectable on/off
PRELIMINARY PRODUCT INFORMATION
5
STEL-1109
INTRODUCTION
The STEL-11091 is a highly integrated, maximally flexible, burst transmitter targeted to the cable modem market. It receives serial data, randomizes the data, performs FEC and differential encoding, maps the data to a constellation before modulation, and outputs an analog RF signal. The STEL-1109 is the latest in a series of modulator chips that comprise the STEL-1103 through STEL-1108 modulators. Several key components (e.g., a 10-bit DAC, FECs, etc.) have been incorporated in the STEL-1109 and the enhancements have resulted in significant changes to the chipOs electrical and software interfaces. The STEL-1109 is capable of operating at data rates of up to 10 Mbps in BPSK mode, 20 Mbps in QPSK mode, and 40 Mbps in 16QAM mode. It operates at clock frequencies of up to 165 MHz, which allows its internal, 10-bit Digital-to-Analog Converter (DAC) to generate RF carrier frequencies of 5 to 65 MHz. The STEL-1109 also uses digital FIR filtering to optimally shape the spectrum of the modulating data prior to modulation. This optimizes the spectrum of the modulated signal, and minimizes the analog filtering required after the modulator. The filters are designed to have a symmetrical (mirror image) polynomial transfer function, thereby making the phase response of the filter linear. This also eliminates the inter-symbol interference that results from group delay distortion. In this way, it is possible to change the carrier frequency over a wide frequency range without having to change filters, thus providing the ability to operate a single system in many channels. The STEL-1109 can operate with very short gaps between transmitted bursts to increase the efficiency of TDMA systems. The STEL-1109 (as well as the STEL1103 and STEL-1108) operates properly even when the interburst gap is less than four (4) symbols (half the length of the FIR filter response). In this case the postcursor of the previous burst overlaps and is superimposed on the precursor of the following burst. Signal level scaling is provided after the FIR filter to allow the STEL-1109Os maximum arithmetic dynamic range to be utilized. Signal levels can be changed over a wide range depending on how the device is programmed. In addition, the STEL-1109 is designed to operate from a 3.3 Vdc power supply and the chip can be interfaced with logic that operates at 5 Vdc.
1
The STEL-1109 utilizes advanced signal processing techniques which are covered by U.S. Patent Number 5,412,352.
STEL-1109
6
PRELIMINARY PRODUCT INFORMATION
PIN CONFIGURATION
The STEL-1109 input and output signal pin assignments are listed in Table 2. The location of the pin numbers is shown by Figure 16 (page 39). The STEL-1109 power supply pins are described in the following paragraph.
Table 2. I/O Signal Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD DATA4 DATA5 DATA6 DATA7 VSS VSS ADDR5 ADDR4 ADDR3 VDD ADDR2 ADDR1 ADDR0 VSS VSS TSDATA DATAEN TCLK FCWSEL0 [7] [20] [20] [20] [20] [7] [7] [20] [20] [20] [7] [20] [20] [20] [7] [7] [9] [10] [9] [21] (S) (B) (B) (B) (B) (S) (S) (I) (I) (I) (S) (I) (I) (I) (S) (S) (I) (I) (I) (I) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 FCWSEL1 VSS VSS VSS VDD CLKEN VSS CLK RDSLEN VDD 5VDD SCRMEN VSS VSS CKSUM VSS ACLK VDD [21] [7] [7] [7] [7] [9,20] [7] [20] [10] [7] [7] [10] [7] [7] [12] [7] [20] [7] (I) (T) (T) (T) (S) (I) (S) (I) (I) (S) (I) (I) (S) (T) (O) (S) (O) (S) (O) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS VSS VSS VSS VSS AV DD OUT OUTN AV SS VDD SYMPLS VSS VSS VSS VSS VSS VSS VSS [7] [20] [7] [7] [7] [7] [7] [7] [7] [7] [7] [20] [20] [7] [7] [7] [7] [7] [7] [7] (S) (O) (S) (T) (T) (T) (T) (T) (S) (N.C.) (S) (AO) (AO) (S) (N.C.) (S) (T) (T) (T) (T) 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 (O) (S) (T) [#] VSS VDD VDD VSS VDD VSS RSTB VSS VSS DIFFEN NCO LD [7] [7] [7] [7] [7] [7] [20] [7] [7] [13] [21] [20] [20] [20] [7] [20] [20] [20] [20] [7] (T) (S) (T) (S) (T) (S) (I) (T) (S) (I) (I) (I) (I) (I) (S) (B) (B) (B) (B) (S)
CSEL
DSB WR VDD DATA0 DATA1 DATA2 DATA3 VSS
DATAENO [20] BITCLK
[9,20] (O) Legend: (AO) (B) (I) (N.C.)
Notes: 1. Pin 31 is applied to input buffers only. 2. See Package Outline (Figure 16) for pin identification.
Analog Output Bi-directional (I/O) signal Input signal Not Connected
Output signal Source Factory Test Pin Page Reference
POWER SUPPLY PINS
There are three separate power supply systems within the STEL-1109. The primary supply for the digital logic circuits is nominally 3.3 volts and is input on the VDD pins. The digital inputs have a separate supply, 5VDD, which can be connected to a 5 volt supply if the STEL1109 inputs are driven from 5 volt logic. If the logic driving the STEL-1109 is run on 3.3 volts, then the 5VDD pin should be connected to 3.3 volts. The return for both digital supplies is VSS. The DAC has a separate analog power supply and return, AVDD and AVSS. The 3.3 volt AV DD input allows the user to provide a separate well filtered supply for the DAC to prevent spurs that might be created from digital noise on the VDD supply system.
PRELIMINARY PRODUCT INFORMATION
7
STEL-1109
FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS
OVERVIEW
The STEL-1109 is comprised of the Data Path and Control Unit sections shown in Figure 1. The Data Path is comprised of a Bit Sync Block, Bit Encoder Block (i.e.,Ethe Scrambler, Reed-Solomon Encoder, and two Multiplexers shown in Figure 2), Symbol Mapper Block (i.e., the Bit Mapper, Differential Encoder, and Symbol Mapper are shown in FigureE5), two channels (one for I and one for Q), a Combiner, and a 10-bit DAC. Each channel consists of a Nyquist Filter, Interpolation Filter, and Modulator. The Control Unit is comprised of a Bus Interface Unit (BIU), Clock Generator, and NCO. Table 1 summarizes the main features of the circuits described by the remaining paragraphs of this section. The STEL-1109 provides 58, programmable, read/write registers (Configuration Registers). Table 3 provides a graphic representation of the STEL-1109Os Configuration Registers and their data fields. Each register can be selected for a write or read operation using addresses 00H through 39H.
Table 3. STEL-1109 Configuration Register Data Fields
Address (Hex) 08 - 00 28 - 09 29 2A 2B 2C 2D 2E 2F 32-30 35-33 36 37 38 39 DATAENBPB Set To Zero
10
Contents Bit 7 Bit 6 Bit 5 Bit 4 NCO Bit 3
21 18 20 20 20
Bit 2
Bit 1
Bit 0
FIR Filter Coefficients
LSB Sampling Rate Control (see address 39 for MSB) Interpolation Filter Gain Control Set To Zero TCLK Sel. FZSINB
9 19 19
Auxiliary Clock Rate Divider Set To One MOD Set To One CLRFIR Set To Zero
14
Set To Zero Set To Zero
Interpolation Filt. Bypass Set To Zero Bit Mapping
13
Invert I/Q Chan. FIR bypass
18 9
Set To Zero
Set To Zero PN On/Off
9 9
21
Set To Zero
18
PN Code Sel
Symbol Mapping
15
Bit Sync Re-arm
Set To Zero SCRAMBLER Init Registers
11 11 12
SCRAMBLER Mask Registers PPolynomial
13
BypassB
10
S-RS
10
Self-Sync
11 12 10
T K
DATAENSEL Set To Zero
10
RSENBPB TRLSBF
10
RSENSEL LDLSBF
10
SCRMENBPB
SCRMENSEL
10
DiffDCBPB
14
DiffDCSEL
20
14
12
12
MSB Sampling Rate Control (see address 29 for LSB)
Note:
Superscripted numbers are page references where discussion on setting the particular register(s) or bit(s) begins.
STEL-1109
8
PRELIMINARY PRODUCT INFORMATION
DIFFEN TCLK TSDATA BIT Sync Block I[1:0], Q[1:0] DATAEN RDSLEN SCRMEN AVDD 5VDD VDD RST Clock Generator CLKEN CLK COS 2FT NCO LD FCWSEL1-0 DATA7-0 ADDR5-0 DSB WR CSEL Bus Interface Unit Numerically Controlled Oscillator SIN 2FT SAMPLS MASTER CLOCK BITCLK SYMPLS ACLK BIT Encoder Block 4 Symbol Mapper Block I[1:0] 2 Q[1:0] 2 Nyquist Filter Nyquist Filter Interpolating Filter Modulator Interpolating Filter DATAENO 10-Bit DAC
DATA PATH
OUT OUTN
CKSUM
CONTROL UNIT
WCP 52981.c-5/2/97
Figure 1. STEL-1109 Block Diagram
DATA PATH DESCRIPTION
BIT SYNC BLOCK The Bit Sync Block has two functions, latching input data, and synchronizing the STEL-1109 BITCLK and symbol counters to the user data. Latching Input Data Latching of input data is accomplished in three ways: * Externally supplied TSDATA is latched by the internal BITCLK. Table 4. Data Latching Options
Data Source TSDATA TSDATA PN Code 10, 3 PN Code 23, 18 Latched By BITCLK TCLK BITCLK BITCLK Register 2C Bit 7 0 1 0 0 Register 2D Bits 1,0 X,0 X,0 0,1 1,1 Mode Name Master Mode Slave Mode Test Mode Test Mode
* *
Externally supplied TSDATA is latched by an externally provided TCLK Internally generated PN code data is latched by the internal BITCLK
See Table 4 for register settings to implement each mode.
PRELIMINARY PRODUCT INFORMATION
9
STEL-1109
BITCLK latches data on its falling edge. TCLK latches data on its rising edge. Whenever the CLKEN input is low, the BITCLK output will stop. In order to provide customers with a continuous clock, the STEL-1109 provides an auxiliary clock (ACLK) output which is discussed later in the clock generator section. The ACLK output is primarily for use in master mode where users may need a clock to run control circuits during the guard time between bursts. When using slave mode, the data that is latched by the rising edge of TCLK is re-latched internally by the next falling edge of BITCLK which re-synchronizes the data to the internal master clock. Synchronizing BITCLK / SYMPLS The synchronization circuit aligns the STEL-1109 BITCLK and its SYMPLS counter circuits to the beginning of the first user data symbol. The circuit has two parts, an arming circuit and a trigger circuit. Once armed, the first rising edge on the TCLK input will activate (trigger) the synchronization process. The circuit can be armed in two ways; taking CLKEN from low to high, or toggling Configuration Register 2EH bit 0 from low to high to low again. In a normal burst mode application, the circuit is automatically rearmed between bursts because CLKEN goes low. For applications that will not allow CLKEN to cycle low between bursts, some system level precautions should be observed to maintain synchronization of user data to the STEL-1109 BITCLK. Once triggered, the sync circuit re-starts the BITCLK and SYMPLS counters. The BITCLK output starts high, and SYMPLS resets to the start of a symbol. There is a delay equal to about three cycles of the master clock from the rising edge of the TCLK input before this restart occurs. During this brief delay period, the BITCLK and SYMPLS counters are still free running and may or may not have transitions. In master mode, the rising edge of TCLK normally marks the transition of the first user data bit (which will be latched in by the next falling edge of BITCLK). In slave mode, the first user data bit must already be valid at this first rising edge of TCLK.
BIT ENCODER BLOCK The Bit Encoder Block consists of a Scrambler, a Reed-Solomon Encoder, and data path controls (multiplexers), as shown in Figure 2.
SCRMEN
Input Multiplexer
Output Multiplexer
SERIAL DATA DATAEN
Scrambler
ENCODED SERIAL DATA
Reed-Solomon Encoder
RDSLEN S-RS
CHKSUM SIGNAL
WCP 52982.c-4/26/97
Figure 2. Bit Encoder Functional Diagram
Data Path Control (Multiplexers)
The STEL-1109 provides a great deal of flexibility and control over the routing of data through or around the encoding functions. With appropriate register selections, data can be routed around (bypass) both encoders, through either one and around the other, through the scrambler then the RS Encoder, or through the RS Encoder and then the scrambler. Control over the bypassing can be set for software control or external (user) input signal control. Generally, if an encoding function will be left either on or off continuously, then software control is appropriate. If the function must be turned on and off dynamically (typically in order to send the preamble Oin the clearO i.e. unencoded), then external (user) input control is required. If the ReedSolomon encoder will not be used at all, then a separate bypass option can be activated to remove an 8 bit delay register from the data path that is required if the possibility of turning on the encoder exists. Each of the external (user) input control pins (if enabled) turns on the encoding function when high and bypasses the function when low. The DATAEN input signal determines whether or not data will advance (shift through) the encoding blocks. The presence of a high on the DATAEN input when the BITCLK output goes low allows the circuits to advance data through them. The DATAEN signal is delayed
STEL-1109
10
PRELIMINARY PRODUCT INFORMATION
internally to allow the rising edge of DATAEN to coincide with the first rising edge of TCLK.
See Table 5 for a summary of register settings required to achieve the various data path possibilities.
Table 5. BIT Encoding Data Path Options
Data Path Data stopped (continuously) Data path on (continuously) Data path enabled by pin 18 Scrambler off (continuously) Scrambler on (continuously) Scrambler enabled by pin 32 RS Encode off (continuously) RS Encode on (continuously) RS Encode enabled by pin 29 Scrambler then RS Encoder RS Encoder then Scrambler Bypass RS Encoder Register 36 Bits 6,5 X,X X,X X,X X,X X,X X,X 1,X 1,X 1,X 1,1 1,0 0,X Register 38 Bits 7-2 01 XXEXX 11 XXEXX X0 XXEXX XX XX 01 XX XX 11 XX XX X0 XX 01 XX XXE11 XX XXEX0 XX XXEXXEXX XXEXXEXX XXEXXEXX
Scrambler
The scrambler can be used to randomize the serial data in order to avoid a strong spectral component that might otherwise arise from the occurrence of repeating patterns in the input data. The Scrambler (Figure 3) uses a Pseudo-Random (PN) generator to generate a PN code pattern. All 24 registers are presettable and any combination of the registers can be connected (tapped) to form any polynomial of up to 24 bits. The scrambler may be either frame synchronized or self synchronized. Table 6 shows the registers involved. The value in the INIT registers is loaded into the scrambler shift registers whenever the scrambler is disabled. The scrambler will scramble data one bit at a time at each falling edge of BITCLK that occurs while both the scrambler and DATAEN are active (enabled). Internal delays on the SCRMEN control signal input allow for a rising edge to occur coincident with the rising edge of BITCLK that precedes the latching of the first data bit to be scrambled.
24-bit Mask Reg 24-bit INIT Reg 24-bit Shift Reg 1 2 3 22 23 24 1 1 2 2 3 3 22 23 22 23 24 24
XOR
SCRMEN SERIAL INPUT
AND
SERIAL OUTPUT
XOR
SELF SYNC MUX
FRAME SYNC
SSYNC
WCP 52983.c-4/26/97
Figure 3. Scrambler Block Diagram
Table 6. Scrambler Parameters
Parameter Generator Polynomial (Mask Reg) Seed (INIT Reg) Scrambler Type Scrambler Characteristic p(x) = c24x 24 + c23x 23 + E + c1 x + 1 where ci is a binary value (0, 1) Any 24 bit binary value, s24-1 Frame synchronized (sidestream) Self-synchronized Configuration Register Setting Register 34 Register 33 Register 35 Bit 7 to Bit 0 Bit 7 to Bit 0 Bit 7 to Bit 0 to c17 c16 to c9 c8 to c1 c24 Register 32 Bit 7 to Bit 0 s24 to s17 Register 36 Bit 4 Set to zero Register 36 Bit 4 Register 31 Bit 7 to Bit 0 s16 to s9 Register 30 Bit 7 to Bit 0 s8 to s1
PRELIMINARY PRODUCT INFORMATION
11
STEL-1109
Type
Set to one
The Mask, Init, and SSync fields can be programmed for different scrambler configurations. For example, the DAVIC Scrambler configuration shown in FigureE4 can
be implemented by programming the Mask, Init, and SSync fields with the values indicated by Table 7.
Table 7. Sample Scramble Register Values
Parameter Generator Polynomial (Mask Reg) Seed (INIT Reg) Scrambler Type Characteristic p(x) = x 15 + x 14 + 1 Configuration Register Setting Register 35 Register 34 Register 33 Bit 7 to Bit 0 Bit 7 to Bit 0 Bit 7 to Bit 0 0000E0000 0110E0000 0000E0000 Register 32 Bit 7 to Bit 0 0000E0000 Register 36 Bit 4 Set to zero Register 31 Bit 7 to Bit 0 0000E0000 Register 30 Bit 7 to Bit 0 1010 1001
0000A9 Hex
Frame synchronized (sidestream)
Reed-Solomon Encoder
The STEL-1109 uses a standard Reed-Solomon (RS) Encoder for error correction encoding of the serial data stream. When DATAEN is high and the RS Encoder is enabled, the serial data stream both passes straight through the RS Encoder and also into encoding circuitry. The encoding circuitry computes a checksum that is 2T bytes long for every k bytes of input data. After the last bit of each block of k bytes of input data, the RS Encoder inserts its checksum (2T bytes of data) into the data path. There is no adverse effect to letting TCLK or TSDATA continue to run during the checksum; the data input will be ignored. CKSUM (pin 35) will be asserted high to indicate that the checksum bytes are being inserted into the data stream and will be lowered at the end of the checksum data insertion. The width of the CKSUM pulse is 2T bytes. The STEL-1109 registers include two bits for determining the bit order for data into and checksum out of the RS Encoder circuitry. Set these to match the Reed-Solomon decoding circuitry along with the other parameters. The error correction encoding uses GF (256) and can be programmed for an error correction capability of 1 to 10, a block length of 3 to 255, and one of two primitive polynomials using the data fields listed in Table 8.
1 1 0 2 0 3 1 4 0 5 1 6 0 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15
EX-OR
AND EX-OR
Randomized Data
Enable
Clear Data Input
WCP 52984.c-4/26/97
Figure 4. DAVIC Scrambler
STEL-1109
12
PRELIMINARY PRODUCT INFORMATION
Table 8. Reed-Solomon Encoder Parameters
Field Name PP Configuration Register 36H (bit 7) 0 p(x) = x8 + x 4 + x 3 + x 2 + 1 1 p(x) = x8 + x 7 + x 2 + x + 1 T K LDLSBF TRLSBF Notes: 1. GF (256). 2. Code generator polynomial 1 is used when PP=0: 36H (bits 3-0) 37H (bits 7-0) 39H (bit 4) 39H (bit 5) 4-bit field for setting Error Correction Capability. Programmable over the range of 1 to 10. 8-bit field for setting User Data Packet Length (K) in bytes. Programmable over the range of 1 to (255 - 2T). [ Net block length, N = K + 2T ] Determines whether the first bit of the serial input is to be the MSB (bit 4 = 0) or LSB (bit 4 = 1) of the byte applied to the RS Encoder. Determines whether the MSB (bit 5 = 0) or LSB (bit 5 = 1) of the RS Encoder checksum byte is to be the first bit of the serial output data. Description 1-bit field for selecting Primitive Polynomial:
G(x) = G(x) =
119 + 2T i =120 2T -1 i=0
(x - ) = 02H
i i
3.
Code generator polynomial 2 is used when PP=1.
(x - ) =
Bit Mapper
02H
SYMBOL MAPPER BLOCK The Symbol Mapper Block (Figure 5) maps the serial data bits output by the Bit Encoder Block to symbols, differentially encodes the symbols, and (in 16QAM) maps the symbols to one of five constellations. The Symbol Mapper Block functions are modulation dependent. The modulation mode also defines the number of bits per symbol. The Symbol Mapper Block outputs 2 bits for each symbol to each of the two Nyquist (FIR) Filters.
I[1:0]** Q[1:0]** Bit Mapper 4 Differential Encoder 4 Symbol Mapper I[1:0]* Q[1:0]* 2 I[1:0]
The Bit Mapper receives serial data and maps the serial data bits to output symbol bits (I1** , I0**, Q1**, and Q0** ). There are four output bits per symbol even in BPSK and QPSK modes. In BPSK, all bits are set equal to each other. In QPSK, each input symbol bit drives a pair of output bits. The four symbol bits are routed to the Differential Encoder in parallel. For BPSK modulation, each bit (symbol = b0 ) of the input serial data stream is mapped directly to I1**, Q1** , I0**, and Q0 ** (i.e., I1** = I0 **= Q1** = Q0 **= b 0 ). Thus, bit mapping has no affect on the respective value of the symbolOs four bits, as shown in Table 9. For QPSK modulation, each pair of bits (a dibit) forms a symbol (b0 b1 ). The QPSK dibit is mapped so that I1*E=EI0** and Q1** = Q0**, as shown in Table 9. For 16QAM, every four bits (a nibble) forms a symbol (b0b 1b 2b 3). The 16QAM nibble is mapped to I 1** , Q1**, I0**, and Q0**, as shown in Table 9.
ENCODED SERIAL DATA 1 DIFFEN 1
Q[1:0] 2
WCP 52985.c-4/26/97
Figure 5. Mapping Block Functional Diagram
PRELIMINARY PRODUCT INFORMATION
13
STEL-1109
Table 9. Bit Mapping Options
Bit-To-Symbol Mapping b0 b1 b2 Mode ** ** ** ** BPSK I1 Q1 I0 Q0 N/A N/A QPSK I1 ** I0** Q1 ** Q0** N/A QPSK Q1 ** Q0** I1 ** I0** N/A 16QAM I1 ** I0 ** Q1 ** ** ** 16QAM Q1 Q0 I1 ** ** ** 16QAM I0 I1 Q0 ** ** ** 16QAM Q0 Q1 I0 ** ** ** 16QAM I1 Q1 I0 ** ** ** 16QAM Q1 I1 Q0 ** ** ** 16QAM I0 Q0 I1 ** ** ** 16QAM Q0 I0 Q1 ** Note: b0 is the first serial data bit to arrive at the Bit Mapper b3 N/A N/A N/A Q0 ** I0 ** Q1 ** I1 ** Q0 ** I0 ** Q1 ** I1 ** Bit Mapping Mod Mode Register 2D Register 2C bits bits 6-4 3,2 XXX XX0 XX1 000 001 010 011 100 101 110 111 1X 00 00 01 01 01 01 01 01 01 01
Differential Encoder
The Differential Encoder encodes the bits (i.e., I1**, I0** , Q1** , and Q0** ) of each symbol received from the Bit Mapper to determine the output bit values (i.e., I1*, Q1*, I0*, and Q0*), which are routed to the Symbol Mapper. The differential encoder can be either enabled or bypassed under the control of either a register bit or a user supplied control signal (DIFFEN pin 70). The selection between user input pin control or register control is made in another register bit, as shown in Table 10. Table 10. Differential Encoder Control
Level/Value Encoding off (continuously) Encoding on (continuously) Encoding enabled by pin 70 high - enable the Differential Encoder low - disable the Differential Encoder Register 38 Bits 1,0 0,1 1,1 X,0
If differential encoding is enabled, then the results are described below for each modulation type.
BPSK
In BPSK mode, the next output bit is found by XORing the input bit with the current output bit. The result is a 180 degree phase change if the output is high and 0Edegrees if the output is low.
QPSK
In QPSK mode, the next output dibit is found by XORing the input dibit with the current output dibit. Table 11 shows the results of the differential encoding performed for QPSK modulation and the resulting phase shift. In the table, I = I1 = I0 and Q = Q1= Q0.
16QAM
In 16QAM mode, the differential encoding algorithm is the same as in QPSK. Only the two MSBOs, I 1** and Q1** are encoded. The output bits I 0* and Q 0* are set equal to the inputs bits I0** and Q0** .
For any modulation mode, if differential encoding is disabled then: I1*Q1*I0*Q0*E=E I1**I0**Q1** Q0**
STEL-1109
14
PRELIMINARY PRODUCT INFORMATION
Table 11. QPSK Differential Encoding and Phase Shift
Current Input (IQ) 00 Current Output (IQ) 00 01 10 11 01 00 01 10 11 10 00 01 10 11 11 00 01 10 11 Next Output (IQ) 00 01 10 11 01 11 00 10 10 00 11 01 11 10 01 00 Phase Shift (degrees) 0 -90 (CW) 90 (CCW) 180 -90 (CW) 180 0 90 (CCW) 90 (CCW) 0 180 90 (CCW) 180 90 (CCW) -90 (CW) 0
Symbol Mapper
The Symbol Mapper receives I1*, Q1*, I 0*, Q0 * of each symbol. Based on the signal modulation and the symbol mapping selection, the Symbol Mapper block maps the symbol to a constellation data point (I1,Q1,I0 ,Q 0 ). The Symbol Mapping field (bits 7-5 of Configuration Register 2EH) will map the four input bits to a new value, as indicated in Table 12. For BPSK and QPSK, the settings of the symbol to constellation mapping bits is ignored. The constellations for BPSK (Figure 6) and QPSK (Figure 7) are shown below. I1Q1 values are indicated by large, bold font (00 and 11) and I0Q0 values by the smaller font (00 and 11).
Q
11
3
11
1 -3 -1 1 3
I
-1
00
-3
00
WCP 52999.c-10/29/97
Figure 6. BPSK Constellation
PRELIMINARY PRODUCT INFORMATION
15
STEL-1109
Q
01
3
Q
11
10 00 10 00
10
01
1 -3 -1 1
11
11
3
-3
00
01
-1 1
11
01
1 3
I
10
-1
I
00 10 00
00
00
-3
10
10
11
WCP 52986.c-10/29/97
11
01 11
01
01
WCP 52987.c-10/29/97
Figure 7. QPSK Constellation
Figure 8. Natural Mapping Constellation Table 12. Symbol Mapping Selections
Mapping Selection Natural Gray DAVIC Left Right Register 2E Bits 7-5 0XX 100 101 110 111
16QAM
For 16QAM modulation, the Symbol Mapper maps each input symbol to one of the 16QAM constellations. The specific constellation is programmed by the Symbol Mapping field (bits 7-5 of Configuration Register 2E H) to select the type of symbol mapping. If the MSB of the Symbol Mapping field is set to 0, the mapping will be bypassed and I 1Q1I0Q0 = I1 * Q 1*I0*Q0 * . The resulting constellation (Figure 8) is the natural constellation for the STEL-1109. If the MSB of the Symbol Mapping field is set to 1, bits 6-5 can select any of four possible types of symbol mapping (Gray, DAVIC, Left, or Right), as indicated by Table 12. Table 13 summarizes the symbol mapping and the resulting constellations are shown in Figure 8 and Figure 9. In these figures, I1Q1 are indicated by large, bold font (00, 01, 10, and 11) and I0Q0 by the smaller font (00, 01, 10, and 11).
STEL-1109
16
PRELIMINARY PRODUCT INFORMATION
Table 13. Symbol Mapping
Input Code Natural Mapping (Bypass) I 1 * Q1* I0 * Q0 * 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output Code I 1 Q1 I0 Q0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Gray I 1 * Q1* I0 * Q0 * 0011 0010 0001 0000 0110 0111 0100 0101 1001 1000 1011 1010 1100 1101 1110 1111
DAVIC I 1 * Q1* I0 * Q0 * 0011 0001 0010 0000 0110 0111 0100 0101 1001 1000 1011 1010 1100 1110 1101 1111
Left I 1 * Q1* I0 * Q0 * 0011 0010 0001 0000 0101 0111 0100 0110 1010 1000 1011 1001 1100 1101 1110 1111
Right I 1 * Q1* I0 * Q0 * 0011 0001 0010 0000 1010 1011 1000 1001 0101 0100 0111 0110 1100 1110 1101 1111
Q
11 01 01 11
11 10
Q
01 11
01
10
-3
11
00
-1 1
10
10
01
-3
00
00
-1 1
00
00
1
3
1
3
10
I
10 00 00 10
10 00 00 01
I
00
11 01 01
10
11
WCP 52988.c-10/29/97
11
11 01 10
01
11
WCP 52989.c-4/26/97
Figure 9. Gray Coded Constellation
Figure 10. Left Coded Constellation
PRELIMINARY PRODUCT INFORMATION
17
STEL-1109
NYQUIST FIR FILTER
Q
11 01 10 11
10
10
-3
00
00
-1 1
00
1
3
01
I
01 00 00 10
The finite impulse response (FIR) filters are used to shape each transmitted symbol pulse by filtering the pulse to minimize the sidelobes of its spectrum. The Symbol Mapper Block outputs the I1I0 data to a pair of I-channel FIR filters and the Q1Q0 data to a pair of Q-channel FIR filters. Figure 13 shows the filter block diagram for a channel pair (I or Q). The FIR filter can be bypassed altogether or, in BPSK or QPSK modes, individual channels can be turned on and off which changes the effective filter gain. Table 14 shows the various FIR configuration options. Table 14. FIR Filter Configuration Options
Mode No FIR Filter 16QAM BPSK/QPSK BPSK/QPSK BPSK/QPSK Gain N/A Unity Unity x2 x3 Register 2E Bits 4-1 XXXX 1010 0000 1111 1010 Register 2C Bit 1 1 0 0 0 0
11
11 10 01
10
11
WCP 52990.c-4/26/97
Figure 11. DAVIC Coded Constellation
Q
11 01 10 11
01
10
-3
00
00
-1 1
00
1
3
01
I
01 00 00 10
Each of the 32 -tap, linear phase, FIR filters use 16Eten-bit, coefficients, which are completely programmable for any symmetrical (mirror image) polynomial. The FIR filter coefficients are stored in addresses 09H - 28H, using two addresses for each 10-bit coefficient as shown in Table. The coefficients are stored as TwoOs Complement numbers in the range -512 to +511 (200H to 1FF H). The filter is always constrained to have symmetrical coefficients, resulting in a linear phase response. This allows each coefficient to be stored once for two taps, as shown in Table 15. Table 15. FIR Filter Coefficient Storage
MSB (Bits 9-8) 0A H 0CH 0EH 10H E E 22H 24H 26H 28H Note: LSB (Bits 7-0) 09H 0BH 0DH 0F H E E 21H 23H 25H 27H Filter Taps Taps 0 and 31 Taps 1 and 30 Taps 2 and 29 Taps 3 and 28 E E Taps 12 and 19 Taps 13 and 18 Taps 14 and 17 Taps 15 and 16
11
11 10 01
10
11
WCP 52991.c-4/26/97
Figure 12. Right Coded Constellation
For MSB storage, only bits 1-0 are used.
STEL-1109
18
PRELIMINARY PRODUCT INFORMATION
I1/Q1
FIR
X2
COEFFICIENT M U 0X 1
1M U 0X
L O G I C
OUT
I0/Q0
FIR
momentary OhitsO of broad band spectral noise, then the digital gain is too high. The interpolation filter gain is the first place to adjust gain because it does not directly affect the shape of the signal spectrum and it has a very wide adjustment range. Overall, gain can affected in the FIR filter function, the interpolation gain function, and by the number of interpolation stages (and therefore accumulators) used. Normally, three interpolation stages are used, but there is a bypass option for use when the interpolation is very high. It should be used only as a last resort after all other gain reduction options have been exercised because of the severe impact to spurious performance. The register bits that affect the interpolation filter functions are shown inTable 16 and Table 17. Table 16. Interpolation Filter Bypass Control
Number of Interpolation Stages Selected 3 2 2 1 Interpolation Filter Bypass Register 2B Bits 5,4 0E0 0E1 1E0 1E1
CLRFIR BYPASS
2
WCP-52992.c-4/26/97
Figure 13. Nyquist FIR Filter INTERPOLATING FILTER The Interpolating Filter, shown in Figure 14, is a configurable, three-stage, interpolating filter. The filter increases the STEL-1109Os sampling rate (to permit the wide range of RF carrier frequencies possible) by interpolating between the FIR filter steps at the master clock frequency. This smoothes the digital representation of the signal which removes spurious signals from the spectrum.
Data Enable
Table 17. Interpolation Filter Signal Level Control
Bypass 16 Sample Clock 3-Stage Differentiator 16 G a i n 32 3-Stage Integrator 11 2
Gain Factor (Relative) 20 21 2 2 2 2
WCP 52993.c-5/2/97
Filter Gain Control Register 2A Bits 7-4 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
2 3 4
Gain Control
4
25
6 7 8
Master Clock
2 2 2 2 2
Figure 14. Interpolation Filter Block Diagram The interpolation filter contains accumulators. As the interpolation ratio grows larger, the number of accumulations per period of time increases. If the interpolation ratio becomes too large, the accumulator will overflow which will destroy the output spectral characteristics. To compensate for this, the interpolation filter has a gain function. This gain is normally set empirically. If the output spectrum is broad band noise or if it appears correct but has regular
29
10 11 12
2 13 2 14 2
15
PRELIMINARY PRODUCT INFORMATION
19
STEL-1109
MODULATOR
The interpolated I and Q data signals are input from the Interpolation Filter, fed into two complex modulators, and multiplied by the sine and cosine carriers which are generated by the NCO. The I channel signal is multiplied by the cosine output from the NCO and the Q channel signal is multiplied by the sine output. The resulting modulated sine and cosine carriers are applied to an adder and either added or subtracted together according to the register settings shown in Table 18. This provides control over the characteristics of the resulting RF signal by allowing either or both of the two products to be inverted prior to the addition. Data Enable Output. The DATAENO output pin is a modified replica of the DATAEN input. DATAENO is asserted as a high 2 symbols after DATAEN goes high and it is asserted as a low 13 symbols after DATAEN goes low. In this way, a high on the DATAENO line indicates the active period of the DAC during transmission of the data burst. However, if the guard time between the current and next data burst is less than 13 symbols, then the DATAENO line will be held high through the next burst. Table 18. Signal Inversion Control
Output of Adder Block Sum = I . cos(t) + Q . sin(t) Sum = I . cos(t) + Q . sin(t) Sum = I . cos(t) Q . sin(t) Sum = I . cos(t) Q . sin(t) Invert I/Q Channel Register 2B Bits 1,0 0E0 0E1 1E0 1E1
CONTROL UNIT DESCRIPTION
BUS INTERFACE UNIT The Bus Interface Unit (BIU) contains the Configuration Registers (58 programmable 8-bit registers). The Reset ( RST ) input signal is the master reset for the STEL-1109. Asserting a low on RST will reset the contents of all Configuration Registers to 00H (as well as clearing the data path registers). Asserting a high on RST enables normal operation. After power is applied and prior to configuring the STEL-1109, a low should be asserted on RST . Since RST is asynchronous, the CLKEN input should be held low whenever RST is low. The parallel address bus (ADDR5-0) is used to select one of the 58 Configuration Registers by placing its address on the ADDR 5-0 bus lines. The data bus (DATA7-0) is an 8-bit, bi-directional data bus for writing data into or reading data from the selected Configuration Register. The access operation is performed using the control signals DSB , CSEL, and WR. The Chip Select ( CSEL) input signal is used to enable or disable access operations to the STEL-1109. When a high is asserted on CSEL, all access operations are disabled and a low is asserted to enable the access operations. The CSELinput only affects Configuration Register access and has no effect on the data path. The Data Strobe ( DSB ) input signal is used to write the data that is on the data bus (D A T A 7-0 ) into the Configuration Register selected by ADDR 5-0. The Write/Read ( WR) input signal is used to control the direction of the Configuration Register access operation. When WR is high, the data in the selected Configuration Register is output onto the DATA7-0 bus. When WR is low, the rising edge of DSB is used to latch the data on the DATA 7-0 bus into the selected Configuration Register. (Refer to the Write and Read Timing diagrams in the Timing Diagrams section.) Some of the Configuration Register data fields are used for factory test and must be set to specific values for normal operation. These values are noted in Table 3. CLOCK GENERATOR The timing of the STEL-1109 is controlled by the Clock Generator, which uses an external master clock (CLK) and programmable dividers to generate all of the internal and output clocks. There are primarily two
10-BIT DAC
The 10-bit Digital-to-Analog Converter (DAC) receives the modulated digital data and the Master clock. The DAC samples the digital data at the rate of the Master clock and outputs a direct analog RF signal at a frequency of 5 to 65 MHz. The DAC outputs, OUT and OUTN, are complementary current sources designed to drive double terminated 50 or 75 (25 or 37.5 total) load to ground. The nature of digitally sampled signals creates an image spur at a frequency equal to the Master Clock minus the output RF frequency. This image spur should be filtered by a user supplied low pass filter. For best overall spurious performance, the gain of the STEL-1109 should be the highest possible (before digital overflow occurs - see Interpolation Filter discussion).
STEL-1109
20
PRELIMINARY PRODUCT INFORMATION
clock systems, the auxiliary clock and the data path timing signals (bit, symbol, and sampling rate signals). The auxiliary clock (ACLK) output is primarily for use in master mode where users may need a clock to run control circuits during the guard time between bursts (when CLKEN is low and BITCLK has stopped). The output clock rate is set by the frequency (fCLK ) of the external master clock and the value (N) of the Auxiliary Clock Rate Control field (bits 3-0 of Configuration Register 2AH). The clock rate is set to: ACLK =
duty cycle for BPSK and QPSK modes. It also has a 50% duty cycle in 16QAM mode when N+1 is even. If N+1 is odd, then BITCLK will be high for (N/2)+1 clocks and then low for N/2 clocks. (Refer to the Bit Clock Synchronization Timing diagram in the Timing Diagrams section.) The BITCLK frequency is determined by :
K = 1 for 16QAM, 2 for QPSK, 4 for BPSK 3 N 4095
BITCLK =
fCLK N +1 2 N 15
NCO
CLK (N+1) K
If N is set to 1 or 0, the ACLK output will remain set high, thereby disabling this function. If the ACLK signal is not required, it is recommended that it be set in this mode to conserve power consumption. The ACLK output is a pulse that will be high for 2 cycles of C L K and low for (N-1) CLK cycles. Unlike other functions, the ACLK output is not affected by CLKEN. The data path timing is based on the ratio of the master clock frequency to the symbol data rate. The ratio must be a value of four times an integer number (N+1). The value of N must be in the range of 3 to 4095. This value is represented by a 12 bit binary number that is programmed by LSB and MSB Sampling Rate Control fields [Configuration Register 29H (LSB) and bits 3-0 of Configuration Register 39 H (MSB)], which sets the SYMPLS frequency [based on the frequency (fCLK) of the external master clock] to: Symbol Rate =
A 24-bit, Numerically Controlled Oscillator (NCO) is used to synthesize a digital carrier for output to the Modulator. The NCO gives a frequency resolution of about 6 Hz at a clock frequency of 100 MHz. The NCO also uses 12-bit sine and cosine lookup tables (LUTs) to synthesize a carrier with very high spectral purity, typically better than -75 dBc at the digital outputs. The STEL-1109 provides register space for three different carrier frequencies. The carrier frequency that will drive the modulator is selected by the FCWSEL 1-0 control pin input signals. A high on the NCO LD input pin causes the registers selected by FCWSEL to drive the NCO at the frequency determined by the register value. The NCOOs frequency is programmable using the NCO field (Configuration Registers 08H -00H). The nine 8-bit registers at addresses 00H through 08 H are used to store the three 24-bit frequency control words FCW OAO, FCW OBO and FCW OCO as shown in Table 19. The output carrier frequency of the NCO (fCARR) will be:
1 fCLK 4 N + 1 3 N 4095
The symbol pulse (SYMPLS) signal output is intended to allow the user to verify synchronization of the external serial data ( TSDATA) with the STEL-1109 symbol timing. SYMPLS is normally low and pulses high for a period of one CLK cycle at the point where the last bit of the current symbol is internally latched by the falling edge of the internal BIT Clock (BITCLK) signal. (Refer to the Timing Diagrams section.) The internal BITCLK period is a function of the MOD field (bits 3-2 of Configuration Register 2CH), which determines the signal modulation. BITCLK has a 50%
fCARR =
fCLK . FCW 224
where, fCLK is the frequency of the CLK input signal. The FZSINB field (bit 7 Configuration Register 2DH) controls the sine component output of the NCO. This can be used in BPSK to rotate the constellation 45 degrees (to Oon axisO modulation). For normal operation, it should be set to one.
PRELIMINARY PRODUCT INFORMATION
21
STEL-1109
Table 19. FCW Selection
FCWSEL1-0 00 01 10 11 FCW Selected FCW A FCW B FCW C Zero Frequency 23 - 16 Register 02H Bits 7 - 0 Register 05H Bits 7 - 0 Register 08H Bits 7 - 0 FCW Value Bits 15 - 8 Register 01H Bits 7 - 0 Register 04H Bits 7 - 0 Register 07H Bits 7 - 0 7-0 Register 00H Bits 7 - 0 Register 03H Bits 7 - 0 Register 06H Bits 7 - 0
STEL-1109
22
PRELIMINARY PRODUCT INFORMATION
TIMING DIAGRAMS
CLOCK TIMING
tCLK
CLK PIN 28 tCLKH tr tf
WCP 52787.c-3/26/97
tCLKL
Table 20. Clock Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol Parameter Clock Frequency ( tCLK tCLKH tCLKL tR tF Clock Period Clock High Period Clock Low Period Clock Rising Time Clock Falling Time
1 t CLK
Min.
Nom.
) 6 2.5 2.5
Max. 165
Units MHz nsec nsec nsec
Conditions
0.5 0.5
nsec nsec
PULSE WIDTH
tCEL
CLKEN PIN 26
tRSTL
RSTB PIN 67
NCO LD PIN 71
tNLDH
WCP 52930.c-4/26/97
Table 21. Pulse Width AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tCEL tRSTL tNLDH Parameter Clock Enable (CLKEN) Low Reset (RSTB) Low NCO Load (NCO LD) High Min. 4 5 1 Nom. Max. Units nsec nsec CLK cycles Conditions
PRELIMINARY PRODUCT INFORMATION
23
STEL-1109
BIT CLOCK SYNCHRONIZATION
CLK PIN 28 CLKEN PIN 26 TCLK PIN 19
tCO tCO 2 (N +1) BPSK (N +1) QPSK See Note 1 N +1 16QAM 2 n = Odd N +2 16QAM 2 n = Even
WCP 52786.c-5/2/97
tCESU
BITCLK PIN 40
See Note 2
Note 1: BITCLK will be forced high on the second rising edge of CLK following the rising edge of TCLK. Note 2: The period of time that BITCLK is high is measured in cycles of CLK (e.g. (N + 1) in QPSK). "N" is a 12 bit binary number formed by taking bits 3-0 of Configuration Register 39 H as the MSB's and taking bits 7-0 of Configuration Register 29H as the LSB's. The BITCLK low period is the same except for 16QAM when "N" is even in which case the low period is (N/2) yielding the correct BITCLK period but not a perfect squarewave.
Table 22. Bit Clock Synchronization AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tCO AUXCLK edge tCESU Clock Enable (CLKEN to TCLK Setup) 3 nsec Parameter Clock to BITCLK, SYMPLS, DATAENO, or Min. Nom. Max. 2 Units nsec Conditions
STEL-1109
24
PRELIMINARY PRODUCT INFORMATION
INPUT DATA AND CLOCK TIMING SLAVE MODE
NOTE 1
MASTER MODE
NOTE 1
TCLK
TCLK
DON'T CARE
BITCLK NOTE 2 DON'T CARE tSU TSDATA tHD
BITCLK
NOTE 3
tCLK tSU tHD
TSDATA
WCP 52935.c -5/2/97
Note 1: Mode is determined by setting of BIT 7 in Configuration Register 2C H. Bit 7 high is slave mode; Bit 7 low is master mode. Note 2: In slave mode, even though BITCLK is shown as ODon't CareO, it should be noted that internally the STELE1109 will relatch the data on the next falling edge of BITCLK. Thus, avoid changing the control signal inputs (DATAEN, DIFFEN, RDSLEN, SCRMEN) at the falling edges of BITCLK. Note 3: In the STEL-1109, data is latched on the rising edge of the CLK that follows the falling edge of BITCLK. Thus, the data validity window is one CLK period (tCLK) delayed. CLK not shown.
Table 23. Input Data and Clock AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tCLK tSU tHD Clock Period TSDATA to Clock Setup TSDATA to Clock Hold Parameter Min. 6 2 2 Nom. Max. Units nsec nsec nsec Conditions
PRELIMINARY PRODUCT INFORMATION
25
STEL-1109
WRITE TIMING
tAVA tWAHD tWASU
Address ADDR[5-0]
tCSHD tCSSU
CSEL Pin 72
tWRSU tWRHD
WR Pin 74
tDSBL tDH tDSU
DSB Pin 73
Data DATA[7-0]
WCP 52717.c-5/2/97
Table 24. Write Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tWASU tWAHD tAVA tCSSU tCSHD tWRSU tWRHD tDSBL tDH tDSU Parameter Write Address Setup Write Address Hold Address Valid Period Chip Select CSEL Setup
Chip Select ( CSEL) Hold
Min. 10 6 20 5 3 5 3 10 1 3
Nom.
Max.
Units nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec
Conditions
Write Setup ( WR) Write Hold ( WR) Data Strobe Pulse Width Data Hold Time Data Setup Time
STEL-1109
26
PRELIMINARY PRODUCT INFORMATION
READ TIMING
tAVA tADV
Address CS
WR
tDICSH tDVCSL tADIV
Data
WCP 52928.c-5/2/97
Table 25. Read Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tAVA tADV tADIV tDVCSL tDICSH Parameter Address Valid Period Address to Data Valid Delay Address to Data Invalid Delay Data Valid After Chip Select Low Data Invalid After Chip Select High 6 2 1 Min. 20 9 Nom. Max. Units nsec nsec nsec nsec nsec Conditions
PRELIMINARY PRODUCT INFORMATION
27
STEL-1109
NCO LOADING (USER CONTROLLED)
OUTPUT
tFCWHD tFCWSU OLD FREQ. NEW FREQ.
FCWSEL1-0 DON'T CARE NCO_LD
NOTE 1
VALID
DON'T CARE tLDPIPE
WCP 52909.c-5/2/97
NCO LOADING (AUTOMATIC)
OUTPUT
ZERO tDENHV SELECTED FREQUENCY ZERO
FCWSEL1-0 DATAENO
DON'T CARE
VALID
DON'T CARE tDENLZ
tDOFCWV tDOFCWI WCP 52909.c-5/2/97
NOTE 1: The first rising edge of CLK after NCO LD goes high initiates the load process. Table 26. NCO Loading AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tLDPIPE Delay tFCWSU tFCWHD tDENLZ tDENHV tDOFCWV tDOFCWI FCWSEL1-0 to NCO-LD Setup FCWSEL1-0 to NCO-LD Hold DATAENO Low to Zero Frequency Out Delay DATAENO High to Valid Frequency Out Delay DATAENO to FCWSEL1-0 Valid DATAENO to FCWSEL1-0 Invalid 10 10 23 23 3 3 CLK cycles CLK cycles CLK cycles CLK cycles CLK cycles CLK cycles Parameter NCO-LD to Change in Output Frequency Pipeline Min. Nom. 23 Max. Units CLK cycles Conditions
STEL-1109
28
PRELIMINARY PRODUCT INFORMATION
DIGITAL OUTPUT TIMING
CLK
tCO tCO tACKH tACKL
AUXCLK Note 1
BITCLK
tCO tSPH
SYMPLS
tCO
DATAENO
tCO tDENOD
WCP 52908.c-5/2/97
NOTE 1:
AUXCLK shown for "n" equal to 2: where n is the 4-bit binary value in Configuration Register 2AH, BITSE3-0.
Table 27. Digital Output Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tCO or AUXCLK edge tACKH tACKL tSPH tDENOD Notes: 1. OnO is the 4 bit binary value in Configuration Register 2AH , bits 3-0. Auxiliary Clock (ACLK) High Auxiliary Clock (ACLK) Low Symbol Pulse (SYMPLS) High BITCLK Low to DATAENO edge 2 (n-1) 1 1 CLK cycles CLK cycles CLK cycles CLK cycles Note 1 Parameter Clock to BITCLK, SYMPLS, DATAENO, Min. Nom. Max. 2 Units nsec Conditions
PRELIMINARY PRODUCT INFORMATION
29
STEL-1109
DATAEN TO DATAENO TIMING
tDENSP
DATAEN
tDIHDO tSPDEN tSPDEN tDLDO tDENSP
DATAENO
SYMPLS
WCP 52910.c-5/2/97
Table 28. DATAEN to DATAENO Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tDIHDO tDLDO tSPDEN tDENSP Notes: 1. Shown for Configuration Register 36H, bit 6=0 (No Reed-Solomon). If bit 6 of Register 36H is a O1O, then the edges of DATAENO will be delayed from those illustrated by 8, 4, or 2 SYMPLS for BPSK, QPSK, or 16QAM, respectively. Parameter DATAEN High to DATAENO High DATAEN Low to DATAENO Low SYMPLS (trailing edge) to DATAEN Setup DATAEN to SYMPLS (trailing edge) Setup 3 5 Min. Nom. 2
nd th
Max.
Units SYMPLS SYMPLS nsec nsec
Conditions Note 1 Note 1
13
BURST TIMING EXAMPLES
The following seven timing diagrams are qualitative in nature and meant to illustrate the functional relationships between the control inputs and signal outputs in various modes of burst operation. Use the key at right to interpret the timing marks. Only the first diagram is of a complete and realistic burst. The remaining diagrams are too short in duration to show DATAENO and CLKEN going low.
Key:
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care. Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing. State Unknown Center Line is HighImpedance "Off" State
WCP 53036.c-5/6/97
STEL-1109
30
PRELIMINARY PRODUCT INFORMATION
SLAVE MODE, QPSK BURST TIMING: FULL BURST
PIN 19 17 26 18 NAME TCLK(1) TSDATA CLKEN DATAEN (A) (B) (C) (D) (E) (L) (L) (H) (M) (N) (I) (K) (F) (G) (J)
39 DATAENO(2) 70 29 32 DIFFEN(3) RDSLEN SCRMEN
Preamble 42 SYMPLS
User Data
Guard Time
WCP 52934.c -5/7/97
NOTES: (1) All input signals shown are derived from TCLK. Each edge is delayed from a TCLK edge by typically 6 to 18 nsec. DATAENO does not depend on TCLK but its edges are synchronized to TCLK. TCLK itself can be turned off after DATAENI goes low. DATAENO shown at its minimum pipeline delay position. This is achieved by setting bit 6 of Configuration Register 36H to zero. Reed-Solomon cannot be used in this mode. If bit 6 is set high, allowing Reed-Solomon an additional pipeline delay of 8Ebits is inserted into the data path. This will shift both edges of DATAENO to the right by 8 cycles of TCLK. If the preamble is not encoded the same as the user data, the DIFFEN control can be toggled in mid transmission as shown. Otherwise, the DIFFEN control can be held high or low depending on encoding desired.
(2)
(3)
(A) First data bit transition on falling edge of TCLK (first of 14 preamble symbols). The data will be valid on the next rising edge of TCLK. (B) CLKEN rises on the same falling edge of TCLK that the data starts on. CLKEN is allowed to rise any time earlier than shown. (C) DATAEN rises on the first rising edge of TCLK (middle of the first preamble bit). (D) DATAENO rises on the falling edge of TCLK (at the end of the second symbol). (E) DIFFEN rises on the rising edge of TCLK one symbol before the first user data symbol. (F) User data bits change on the falling edge of TCLK and must be valid during the next rising edge of TCLK. (G) End of user data. Note that the data is allowed to go away immediately after it is latched in by the rising of TCLK which occurs in the middle of the last user data bit. (H) DIFFEN goes low on rising edge of TCLK (last user data symbol). (I) (J) DATAEN goes low on rising edge of TCLK (on the cycle of TCLK after the last user data bit). CLKEN must stay high until any time on or after the point where DATAENO goes low.
(K) DATAENO stays high until the 13th SYMPLS after DATAEN goes low. (L) RDSLEN and SCRMEN go high on the first rising edge of TCLK in the User Data. (M) RDSLEN goes low on the rising edge of TCLK (last user data symbol). (N) SCRMEN goes low on the rising edge of TCLK (on the cycle of TCLK after the last user data bit).
PRELIMINARY PRODUCT INFORMATION
31
STEL-1109
MASTER MODE, BPSK BURST TIMING SIGNAL RELATIONSHIPS
CLKEN BITCLK TCLK DATAEN TSDATA
GUARD TIME
PI
PI
PI
PI
UI
NOTE 1
UI
UI
UI
GI
GI
GI
GI
PREAMBLE
USER DATA
GUARD TIME
DIFFEN RDSLEN SCRMEN SYMPLS DATAENO
NOTE 2
WCP 52911.c-5/6/97
SLAVE MODE, BPSK BURST TIMING SIGNAL RELATIONSHIPS
CLKEN BITCLK TCLK DATAEN TSDATA DIFFEN RDSLEN SCRMEN SYMPLS DATAENO
NOTE 2 GUARD TIME
PI
PI
PI
PI
UI
UI
NOTE 1
UI
UI
GI
GI
GI
GI
PREAMBLE
USER DATA
GUARD TIME
WCP 52912.c-5/6/97
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring DIFFEN high at the leading edge of the user data packet (dotted line). If bit 6 of Configuration Register 36H is a "1" then the rising edge of DATAENO will be delayed by eight cycles of BITCLK (dotted line). This is required if the Reed-Solomon encoder is used.
NOTE 2:
STEL-1109
32
PRELIMINARY PRODUCT INFORMATION
MASTER MODE, QPSK BURST TIMING SIGNAL RELATIONSHIPS
CLKEN BITCLK TCLK DATAEN TSDATA GUARD TIME DIFFEN RDSLEN SCRMEN SYMPLS DATAENO NOTE 2
WCP 52840.c-5/7/97
PI
PQ
PI
PQ
UI
UQ
UI
UQ
GI
GQ
GI
GQ
PREAMBLE NOTE 1
USER DATA
GUARD TIME
SLAVE MODE, QPSK BURST TIMING SIGNAL RELATIONSHIPS
CLKEN BITCLK TCLK DATAEN TSDATA GUARD TIME DIFFEN RDSLEN SCRMEN SYMPLS DATAENO NOTE 2
WCP 52839.c-5/7/97
PI
PQ PI PREAMBLE
PQ
UI
UQ UI USER DATA
UQ
GI
GQ GI GUARD TIME
GQ
NOTE 1
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring DIFFEN high at the leading edge of the user data packet (dotted line). If bit 6 of Configuration Register 36H is a "1" then the rising edge of DATAENO will be delayed by eight cycles of BITCLK (dotted line). This is required if the Reed-Solomon encoder is used.
NOTE 2:
PRELIMINARY PRODUCT INFORMATION
33
STEL-1109
MASTER MODE, 16QAM BURST TIMING SIGNAL RELATIONSHIPS
CLKEN BITCLK TCLK DATAEN TSDATA
GUARD TIME
PI1 PQ1 PI0 PQ0 PI1 PQ1 PI0 PQ0 UI1 UQ1 UI0 UQ0 UI1 UQ1 UI0 UQ0 GI1 GQ1 GI0 GQ0 GI1 GQ1 GI0 GQ0
PREAMBLE NOTE 1
USER DATA
GUARD TIME
DIFFEN RDSLEN SCRMEN SYMPLS DATAENO
NOTE 2
WCP 52913.c-5/6/97
SLAVE MODE, 16QAM BURST TIMING SIGNAL RELATIONSHIPS
CLKEN BITCLK TCLK DATAEN TSDATA
GUARD TIME
PI1 PQ1 PI0 PQ0 PI1 PQ1 PI0 PQ0 UI1 UQ1 UI0 UQ0 UI1 UQ1 UI0 UQ0 GI1 GQ1 GI0 GQ0 GI1 GQ1 GI0 GQ0
PREAMBLE NOTE 1
USER DATA
GUARD TIME
DIFFEN RDSLEN SCRMEN SYMPLS DATAENO
NOTE 2 WCP 52914.c-5/7/97
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring DIFFEN high at the leading edge of the user data packet (dotted line). If bit 6 of Configuration Register 36H is a "1" then the rising edge of DATAENO will be delayed by eight cycles of BITCLK (dotted line). This is required if the Reed-Solomon encoder is used.
NOTE 2:
STEL-1109
34
PRELIMINARY PRODUCT INFORMATION
ELECTRICAL SPECIFICATIONS
The STEL-1109 electrical characteristics are provided by Table 29 through Table 31.
WARNING
Stresses greater than those shown in Table 29 may cause permanent damage to the STEL-1109. Exposure to these conditions for extended periods may also affect the STEL-1109Os reliability. Table 29. Absolute Maximum Ratings
Symbol T stg VDDmax AV DDmax 5VDDmax AV SS VI(max) Ii PDiss (max) Note: 1. 2. All voltages are referenced to VSS. 5VDD must be greater than or equal to VDD. This rule can be violated for a maximimum of 100 msec during power up. 3. See Duty Cycle Derating Curves (Figure 15) Parameter Storage Temperature Supply voltage on VDD Supply voltage on AVDD Supply voltage on 5VDD Analog supply return for AVDD Input voltage DC input current Power dissipation @ 85oC Range 40 to +125 0.3 to +4.6 0.3 to +4.6 0.3 to +7.0 10% of VDD 0.3 to V DD+0.3 30 690 Units Note 1 C volts volts volts Note 2 volts volts mA mW Note 3
PRELIMINARY PRODUCT INFORMATION
35
STEL-1109
100
Duty Cycle (%)
90 80 70 60 50 25 30 35 40 45 50 55 60 65 70 75 80 85
Ambient Temperature (degrees C)
WCP 52994.c-4/26/97
Figure 15. Duty Cycle Derating versus Temperature (@3.3V) Table 30. Recommended Operating Conditions
Symbol AV DD 5VDD VDD CLOAD RLOAD Parameter Supply Voltage Supply Voltage Supply Voltage DAC Load Capcitance DAC Load Resistance Recommended DAC Load VLOAD Ta Note: 1. 2. All voltages with respect to Vss and assume AV SSE=EVSS If interface logic is to be driven by VDD then connect the 5VDD pin to the VDDEsupply. 3. Duty Cycle derating is required from +70 to +85 degrees. DAC Output Voltage Operating Temperature (Ambient) Range NOTE 1 +3.3 10% +5.0 10% +3.3 10% 20 30K 37.5 1.25 40 to +85 Units volts volts Note 2 volts pF ohms ohms Volts C Note 3
STEL-1109
36
PRELIMINARY PRODUCT INFORMATION
Table 31. DC Characteristics (V DD = 3.3 V +/-10%, VSS = 0 V, Ta = -40 to 85 C)
Symbol IVDDQ IVDD I5VDD IAV DD VIHCLK VILCLK VIH VIL IIH IIL Parameter Supply Current, Quiescent Supply Current, Operational, VDD Supply Current, Operational, 5VDD Supply Current, Operational, AVDD Clock High Level Input Voltage Clock Low Level Input Voltage High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current 2.4
NOTE 3
Min.
Nom.
Max. 1.0 mA
Units
Conditions Static, no clock
1.9 0.2 12.0 2.0 0.8 2.0 0.8 10 10 3.0 0.2 40 VDD 0.4
mA/MHz mA mA volts volts volts volts A A volts volts mA CLK, Logic '1' CLK, Logic '0' Other inputs, Logic '1' Other inputs, Logic '0' VIN = 5V DD VIN = VSS IO = 2.0 mA IO = +2.0 mA VOUT = VDD, VDDE=Emax All inputs All outputs
VOH(min) High Level Output Voltage VOL(max) Low Level Output Voltage IOS CIN COUT IOFS VO RO CO VNO NOTES: 1. 2. Output Short Circuit CurrentE
Input Capacitance Output Capacitance Output Full Scale DAC Current DAC Compliance Voltage (Differential) DAC Output Resistance DAC Output Capacitance DAC Output Noise Voltage Density
2 4 19.2 0.96 10
pF pF mA Volts
TBD TBD TBD
Ohms pF nV Hz
With V SS = AVSS, Noise coupling from supply to the DAC output. Noise coupling to DAC output when noise is common to AVDD and AVSS with respect to VSS of VDD and VSS with respect to AV SS. Specified for digital outputs. The DAC output can survive an indefinite short circuit to AVSS.
3.
PRELIMINARY PRODUCT INFORMATION
37
STEL-1109
RECOMMENDED INTERFACE CIRCUITS
SLAVE MODE INTERFACE
TSDATA CLKEN D Q TSDATA
D
Q
OR
CLKEN DATAENO
DATAEN
D
Q
DATAEN
STEL-1109
DIFFEN
D
Q 2
DIFFEN FCWSEL 1-0 TCLK
WCP 52995.c-5/2/97
FCWSEL 1-0 TCLK
D
Q
MASTER MODE INTERFACE
TSDATA
D
Q
D
Q
TSDATA
BITCLK
DATAEN
D
Q
D
Q
DATAEN
DIFFEN
D
Q
D
Q
DIFFEN
STEL-1109
D
Q
TCLK CLKEN*
WCP 52115.c-5/2/96
* CLKEN may be turned off between bursts to conserve power as long as it is kept on until after DATAENO goes low. Note that the BITCLK output goes inactive whenever CLKEN is low.
STEL-1109
38
PRELIMINARY PRODUCT INFORMATION
EXAMPLE OUTPUT LOAD SCHEMATIC
Iout Pin 52 50 X AVSS 0.1 Ioutn Pin 53 50 MiniCircuits 1:1 0.1 T1-6TKK81 0.1 50 line Note 1 50 load
AVSS
WCP-52997.c-5/6/97
Note 1: Normally some application dependant alias filtering and amplitude control appear at this point in the circuit.
MECHANICAL SPECIFICATIONS
The STEL-1109 is packaged as a single chip. The chipOs package style, dimensions, and pin identification are shown in Figure 16.
0.787" 0.008" 64 65
0.913" 0.008"
41 40
Detail of pins
Top View
0.551" 0.008" 0.677" 0.008" 25 24 0.01" max. 0.029"/ 0.041"
80 1 0.0315" 0.008"
0.012"/0.018" Pin 1 Identifier 0.130" max.
Package style: 80-pin MQFP. Thermal coefficient, ja = 58 C/W
WCP 52998.c-4/26/97
Note:
Tolerance on pin spacing is not cumulative Figure 16. STEL-1109 Mechanical Characteristics
PRELIMINARY PRODUCT INFORMATION
39
STEL-1109
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied Intel may make changes to specifications and product descriptions at any time, without notice.
warranty, relating to sale and/or use of Intel(R) products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
For Further Information Call or Write
INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888 WCP 970156
Copyright (c) Intel Corporation, December 15, 1999. All rights reserved

▲Up To Search▲

Price & Availability of STEL-1109

	To Download STEL-1109 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .